1. Field of the Invention
This invention relates to electronic circuits and, more particularly, to a memory interface circuit, which can be configured for asynchronous and synchronous operation. In addition, the memory interface circuit can be configured for accessing a storage element using one of multiple clock signals available to the memory device.
2. Description of the Related Art
The following descriptions and examples are given as background only.
As shown in FIG. 1, a typically memory device 100 may include an input/output (I/O) block 110, a memory interface 120, and a storage array 130. In some cases, storage array 130 may be implemented with volatile or non-volatile memory storage elements. Types of volatile memory include memory that must be periodically refreshed (e.g., Dynamic Random Access Memory or DRAM) or memory that will lose its programmed state if power is removed (e.g., Static RAM or SRAM). Types of non-volatile memory include memory that maintains its programmed state when power is removed (e.g., Electrically Erasable Programmable Read Only Memory or EEPROM, Flash Magnetic RAM or MRAM, etc.) In other cases, storage array 130 may be implemented as an array of register elements (e.g., an array of flip-flops or latches).
Memory interface 120 is configured for receiving the address, data, clock and/or control signals needed to access storage array 130. In some cases, memory interface 120 may receive the signals from I/O block 110. Access to the storage elements may be performed in a synchronous or asynchronous manner, depending on the signals received and the particular type of storage elements used in the array. In synchronous memory architectures, access to the storage elements is controlled by a clocking signal (e.g., a system clock or memory controller clock). However, no such clocking signal is needed in asynchronous memory architectures, where access is instead coordinated with respect to an asynchronous control signal. Examples of synchronous memory include SRAM and Synchronous DRAM (SDRAM). Examples of asynchronous memory include SRAM and various types of DRAM (e.g., Extended Data Output or EDO and Fast Page Mode (FPM) DRAM).
In most cases, the memory interface may be configured for operating in a synchronous mode or an asynchronous mode, but not both. For example, FIG. 2 illustrates one embodiment of a memory interface 200 configured for operating in asynchronous mode. As shown in FIG. 2, an asynchronous memory interface may include an address latch 210, a storage array 220, a data latch 230, and a self-timed control logic block 240. During read operations, the address (“Address”) and output data (“Out”) are latched with respect to an asynchronous control signal (“Control”). In some cases, the address, data and asynchronous control signal may be supplied to memory interface 120 by a device (e.g., a controller) wishing to gain access to the memory.
FIG. 3 illustrates one embodiment of a memory interface 300 configured for operating in synchronous mode. As shown in FIG. 3, a synchronous memory interface may include an address register 310, a storage array 320, and a data register 330. The use of registered elements enables memory accesses to be coordinated with a clocking signal (“Clock”) supplied to the memory interface. In some cases, an interface clock signal may be used to move information through the memory. For example, a registered address (“Address”) may be latched to storage array 310 upon receiving a first rising edge of the interface clock signal (“Clock”). The data associated with the address may be latched into data register 330 on the next rising edge of the interface clock. In this manner, movement through the memory may be coordinated in sync with the rising (or falling) edge of the interface clock.
Unfortunately, the conventional memory interfaces shown in FIGS. 2 and 3 present many disadvantages. For example, the memory interfaces shown in these figures are only designed to operate in one mode (e.g., synchronous or asynchronous). They do not provide the flexibility of accessing storage elements in either mode. Therefore, the memory interfaces cannot be used alone to provide both synchronous and asynchronous operation in storage arrays (e.g., SRAM) that support both modes of operation. The memory interfaces shown in FIGS. 2 and 3 also require the storage elements to reside in a single clock domain (e.g., the interface clock domain, as discussed above). This prevents the memory interfaces from being used when access to the storage elements is controlled by more than one clock domain (e.g., when a storage array is read from one clock domain and written to from another clock domain).
Therefore, a need exists for an improved memory interface, which may be configured for accessing storage elements in either synchronous or asynchronous mode. An improved memory interface is also needed in which access to the storage elements is provided from substantially any clock domain.